(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming buried contacts having low contact resistance in conjunction with butted contact formation in the fabrication of integrated circuits.
(2) Description of the Prior Art
Referring to FIG. 1, a typical buried contact is formed by depositing a doped layer of polysilicon 16 over and on the planned buried contact region in a semiconductor substrate 10. The buried contact region 20 is doped by outdiffusion of dopants from the doped polysilicon layer 16 into the silicon substrate or by ion implantation into the layer 16. The doped polysilicon layer is allowed to remain on the buried contact region as its contact. The polysilicon 16 is then patterned as shown by photoresist mask 25. During etching of the polysilicon 16, a portion of the semiconductor substrate within the buried contact area will be exposed. The substrate is deliberately exposed to provide a larger contact area for the planned butted contact by making use of the trench sidewall area.
During polysilicon overetching, a buried contact trench 27 will be etched. The trench depth is (A-B)+overetch (to remove polysilicon residue). The trench 27 could be etched deeper than the junction 20. However, the doped polysilicon 38, shown in FIG. 3 will dope the area surrounding the sidewalls of the trench. An oxide layer 30 is deposited over the polysilicon layer 16 and within the contact opening and within the trench 27, as shown in FIG. 2. A second photoresist mask 35 is formed over the substrate with an opening for a planned butted contact.
The oxide layer 30 is etched away where it is not covered by the mask 35. Oxide residue 31 remains within the trench, as shown in FIG. 3. A polysilicon layer 38 forms the butted contact to polysilicon 16 and the substrate active region within the opening. The residual oxide within the trench will cause high contact resistance which is not desirable. Because of the oxide residue, there is less contact area for the junction. The trench sidewall contact area between the polysilicon and the substrate contribute significantly to conductivity. Also, the oxide residue will prevent dopant outdiffusion into the silicon substrate surrounding the sidewalls of the trench. This also will cause high contact resistance.
Overetching of as much as between about 8000 and 12,000 Angstroms is required to remove the oxide residue from the trench to guarantee a good butted contact. It is sometimes necessary to overetch by 400 to 500%. This is expensive. The longer etch time required for overetching means longer equipment processing time and therefore, higher wafer processing costs. It is desired to find a method of forming a trenched butted contact without excessive overetching.
U.S. Pat. Nos. 5,340,774 to Yen and 5,780,331 to Liaw et al teach buried contact processes. U.S. Pat. No. 5,721,146 to Liaw et al teaches forming a buried contact in a trench. U.S. Pat. No. 5,716,881 to Liang et al discloses an SRAM buried contact process. U.S. Pat. No. 5,827,764 shows a butt contact in a buried contact process.